1. Field of the Invention
The present invention relates to an image processing circuit for image data picked up with a digital pickup device such as a digital still camera.
2. Description of the Background Art
FIG. 26 schematically illustrates the structure of a general digital still camera 100. As shown in FIG. 26, an image signal picked up with an image pickup device 105 such as a loaded CCD or CMOS sensor is A/D converted to a digital image signal and thereafter captured by an image processing part 106, to be subjected to various image processing such as pixel interpolation, color space conversion and edge enhancement. The image data subjected to the image processing is displayed on a finder of a liquid crystal monitor 109 or the like. In general, the image pickup device 105 is driven in either an interlacing system of reading image signals from an odd field consisting of only odd lines forming all pixels and an even field consisting of only even lines at temporally different timings or a progressive system of sequentially reading image signals from respective lines. Referring to FIG. 26, numeral 101 denotes an optical lens, numeral 102 denotes a color correction filter, numeral 103 denotes an optical LPF (low-pass filter), numeral 104 denotes a color filter array, numeral 107 denotes a driving part driving/controlling the image pickup device 105 etc., and numeral 111 denotes an external interface connected to an external device.
Operations of the digital still camera 100 are as follows: First, the liquid crystal monitor 109 visually displays image signals slightly reduced in resolution by culling a plurality of prescribed lines from all pixels of the image pickup device 105 and subjected to image processing in the aforementioned image processing part 106 to the operator of the digital still camera 100 through the finder (finder operation).
The operator presses an image pickup button while confirming the image of an object through the liquid crystal monitor 109, so that pixel data are read from all lines of the image pickup device 105 in the interlacing system or the progressive system (all pixel reading operation). The pixel data are A/D converted, subjected to image processing by the image processing part 106, thereafter subjected to JPEG compression or the like and stored in a storage medium such as a built-in memory 108 or a memory card 110. Referring to FIG. 27, pixel data (CCD data) of a first field defined by either an odd field or an even field and subsequently read pixel data of a second field defined by the remaining field are read from the image pickup device 105 driven in the interlacing system, A/D converted and thereafter temporarily stored in a raw image data buffer 108a provided in the built-in memory 108 (step 100). Then, a real-time processing unit (hereinafter abbreviated as an RPU) 120 formed by hardware sequentially reads the pixel data of the first and second fields stored in the raw image data buffer 108a, executes image processing such as pixel interpolation, color space conversion and edge enhancement in real time and outputs the processed data to a processed data buffer 108b, which in turn stores the processed data (step 101). Then, a CPU (central processing unit) 121 reads the processed data from the processed data buffer 108b, performs JEPG (joint photographic experts group) compression or the like by software with a temporary storage data buffer 108c and thereafter stores the processed data in a storage medium 122 such as the aforementioned memory card 110 (step 102).
When the image pickup device 105 is driven in the progressive system, the processing of the aforementioned steps 101 and 102 can be executed by directly outputting the CCD data to the RPU 120 without temporarily storing the same in the raw image data buffer 108a. 
In general, however, the frequency of a driving clock for the image pickup device 105 is suppressed to a constant value within a range not exceeding the maximum value of the driving clock frequency for the RPU 120, to disadvantageously result in a small frame rate for finder display. In other words, a small load is applied to the RPU 120 in the aforementioned finder operation since the image pickup device 105 outputs culled CCD data of low resolution, while the load applied to the RPU 120 is increased to at least twice in the aforementioned all pixel reading operation since the image pickup device 105 outputs CCD data of high resolution from all lines. However, the driving clock frequency for the image pickup device 105 is suppressed to the constant value within the range not exceeding the maximum driving clock frequency allowed for the RPU 120 throughout the periods of the all pixel reading operation and the finder operation, and hence the frame rate for finder display is reduced to deteriorate the quality of the visual image displayed on the finder.